Emerging storage class memory technologies, such as PCM, STT-RAM, etc., fit well in conventional processor-memory hierarchies due to their ability to reduce read latencies. However, the ability of these conventional hierarchies to reduce write latencies continues to be problematic because any delay in performing write operations can directly impact the performance of an application. The ability of these hierarchies to reduce the total number of writes to storage class memory is critical, both from a performance perspective as well as from an endurance perspective.
Similarly, write frequency in the processor memory hierarchy is several orders of magnitude higher than that which is done on the persistence storage. Thus, when storage class memory (SCM) is used as a DRAM replacement or in a hybrid main memory system, it is critical to control the total number of writes as well as limit the write bandwidth requirements.